Built-In Test and Calibration of DAC/ADC Using A Low-Resolution Dithering DAC∗

This paper presents a BIST scheme to test and calibrate on-chip DAC and ADC and to improve both linearity and resolution of converters using a built-in sigma-delta modulator. We use a dithering dynamic element matching (DEM) techniques. A first-order sigma-delta modulator is used to sample DAC outputs because of high linearity of its outputs with high oversampling rate (OSR). The scheme is capable of characterizing non-linearity of DAC/ADC by a polynomial-fitting algorithm to obtain calibration coefficients. A built-in low-cost lowresolution dithering DAC is employed to compensate analog outputs of the on-chip DAC for higher resolution and linearity. Simulation shows that using a 6-bit dithering DAC a 14-bit on-chip DAC could be calibrated with 2bit ENOB gain. Calibration of the on-chip ADC is also discussed.